Welcome Mark and Joe Garrison from Saleae!

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• The idea for Saleae started back in 2005. Prior to it becoming a day job, Joe worked at LeapFrog (not leapmotion).
  
• Saleae now has 9 employees, 3 of which are sw devs.
  
• The new pro logic family was started using crowdfunding.
  
• Chris didn’t like this idea when he heard about it because he thought Saleae was a much bigger company.
  
• There is a great picture of all the members of the team on the about page.
  
• Dave mentioned the Osborn (computer) effect. The 1st rule of sales: sell what you have
  
• Cashflow is super important in business, especially hardware. Saleae got “Net30” from a few distributors but it didn’t always cover the entire part order.
  
• When Apple started, they were able to finagle ridiculous payment terms (Net90 payments for parts, asking for Net10 for payment from customers)
  
• One thing that is lacking for hw companies is good forecasting software. They ended up writing “Saleae ERP” to deal with it.
  
• Saleae does use some CMs, even though there is a desire to bring production in house.  It seems like a good idea because you pay per placement and the Logic Pro 8 has 500 parts (!).
  
• When attempting the in house manufacturing with a new pick and place, they didn’t realize the problems they would have with certain parts. Specifically the 0201 parts. There are also BGA parts on board that didn’t cause too many issues.
  
• Their PnP machine was from Mancorp (who work with addafruit, sparkfun, pololu). Saleae was asking for tighter specs that the equipment wasn’t quite able to hit, causing havoc for production schedules.
  
• For manufacturing in house, Joe recommends:
  
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  • Find other CMs building similar products.
    
  • Build a board on the machine before buying.
    
  • Lease instead of buy if you decide to jump in.
    
  
  
  
• The main problem with the 0201 parts was tombstoning (when a part goes up on one end). This can be cause by things like:
  
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  • Pad size variations.
    
  • Uneven paste.
    
  • Unoptimized heat profiles in the reflow oven.
    
  • Slight misplacement of parts.
    
  
  
  
• Saleae had a vapor phase instead of a traditional reflow oven.
  
• Distributors like Avnet gave them bonded inventory, allowing payment upon receipt (freeing up cashflow).
  
• One of the key points of differentiation is the software: it is built for user friendliness and optimizes for an abundance of resources. The logic triggering is in software.
  
• A few years ago Saleae decided to go cross platform and programming switched from C# to C++.
  
• A large problem with the original Logic and Logic16 was counterfeiting cloning in China. It was due to using the common FX2 chipset but having a great software built on top of it. They prefer Saleae over an open source alternative like SigRok.
  
• Instead of taking the FTDI (and other logic analyzer on the market) route of bricking the counterfeit device, Saleae is hands off with counterfeiters, requesting that customers buy the real thing.
  
• The price of a clone design was about 1/10th the price of a Saleae product.
  
• The key crack was in the bitstream for the FPGA. 2 fans of the company reverse engineered the FPGA over a year’s time and replaced the bitstream in the software loader. There was a post detailing how they did it on Chinese forums.
  
• Saleae attempted to push a change to the firmware to see how fast it got fixed in China. It took 48 hours.
  
• The new Logic and Logic Pro family has many more devices to prevent easy clones, including inside the FPGA.
  
• The FPGA is rather full, actually: The Logic Pro 8 has 2 slices left on the FPGA (a Spartan6 LX9)
  
• At the beginning of development they were attempting to use an IIR filter on the analog signals. In the end, they used a CIC filter.
  
• The sampling is done with a Hittite chip with 8 ADCs internally running at 50msps. Hittite was recently bought by ADI.
  
• Mark learned FPGAs in 2009 and programs the devices in VHDL (because he was learning that at the time).
  
• The key to learning the difference between VHDL/verilog is understanding the delta cycle.
  
• The FPGA clocks mostly at 200MHz and has some higher SERDES clocking onboard for the ADCs.
  
• On the higher end models they use an FX3 to talk USB3.0. It has a 32bit bus running at 100MHz.
  
• Most pins on the Spartan6 can be used with a SERDES module internally (with differential signaling). On higher end Spartan6 parts there are transceivers that can do high speed stuff (6 Gsps+).
  

Many thanks to Mark and Joe for being on the show. It was a great lesson in manufacturing, test equipment, software development and building products!

Image courtesy of Saleae.com